Research Journal of Engineering and Technology

V. Rama Raju ¹, M. Rukmini ², R. Borgohain ³, N. V. Thakor ⁴, R. N. S. K. Kartheek ⁵

Affiliations
1 Gowthami Women Engineering College, Proddatur (Kadapa), IN
2 NIMS Hospital & OUCE, Biomedical Engg. Dept, Hyderabad, IN
3 NIMS Hospital, Hyderabad, IN
4 National University of Singapore, SG
5 SV Govt. Polytechnic, Tirupathi, IN

Abstract

We setup an EMG amplifier for multi channel capturing of EMG signal with special reference to Writer's cramp (WC) from the subject having input impedance greater than 100 MegOhm(M ). By using this setup we gathered EMG- EMG data (signals) from WC subjects (diseased conditions) hand muscles: ECR and ECU, FCR and FCU, followed by fifth muscle using a set-of-five innocuous micro-wire-electrodes (50μ) in each-subject. We then assessed coherence and conducted chi-square (χ²) tests on these data in eight subjects of concordant(C) group and 4 subjects of discordant (D) group of right-hand-writing-signal (RHWS) and in left-hand-writing-signal (LHWS)) studied. We compared the difference between flexor-aspect-of-forearm and extensor-aspect-of-intrinsic hand-muscles. This showed significant coherence in both concordant and discordant groups of WC mirror-movements (MMs) in mirror-Dystonia. These observations suggest that the nature of EMG-EMG coherence in dystonic WC may be constrained by the descendingmotor- systems, both in terms of their anatomical-distribution and their frequency-characteristics. In our computation, the coherence showed symmetry along the diagonals in graphs. We thus state that, this study showed significant quantifiable EMG differences in the signals/waveforms seen while writing with the right and left hands between those WC subjects with concordant MMs (C group) versus those with discordant MMs (D group).

Keywords

EMG-Electromyography, WC-Writer's Cramp, MM-Mirror Movements, Dystonia, Coherence Of EMG, ECR-Extensor Curpi Radialis, ECU-Extensor Curpi Ulnaris, FCR-Flexor Curpi Radialis, FCU-Flexor Curpi Ulnaris, RHWS-Right Hand Writing Signal, LHWS-Left Hand Writing Signal.

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V. Rama Raju ¹, Y. Sri Lakshmi ², E. Brahma Reddy ³

Affiliations
1 ECE & CSE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP, IN
2 ECE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP, IN
3 CSE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP, IN

Abstract

Leakage (or static power consumption) and Glitches are two of the major problems faced by the semiconductor nanometer technologies. This project develops new power minimization methods for digital CMOS circuits considering two components of power, namely, the leakage power and the glitch power are minimized while the overall circuit delay is controlled. Arithmetic circuits like adders and multipliers are essential components in the design of circuits in ASIC. To design low power high sped arithmetic circuits a combination of techniques at four levels is required. They are Algorithm, architecture, circuit and system levels. With the continuous increase of the density and performance of integrated circuits due to the scaling down of the CMOS technology, reducing power dissipation becomes a serious problem that every circuit designer has to face. Digital multiplication is not the most fundamentally complex operation, but is the most extensively used operation. Innumerable schemes have been proposed for realization of the operation. Various multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for lowfrequency applications. A novel practical approach has been set up to investigate the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the TG-multiplier dissipates less energy than other traditional array multipliers. By combining transmission gates with static CMOS in TG-multiplier architecture, a new approach is proposed to improve the energy-efficiency for low-power architectures. The project consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of Vddto- ground paths also contributes to a significant decrease of static consumption.

Keywords

Multipliers, TG Full Adders, 10 Transistor Adders, Low Power Design.

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V. Rama Raju ¹, R. Vaishnavi ²

Affiliations
1 ECE & CSE Dept., SSN College of Engg. & Technology, Ongole, Prakasham-523002, AP, IN
2 Dept of ECE, Vathsalya Institute of Science & Technology (VIST) Anantharam (V), Bhongir , Nalgonda Dist. 508116 AP, IN

Abstract

In this paper, the author derived the Erlang model B and C formulas mathematically and summed up approximately in/with fifty equations or expressions. The result analysis revealed that using signal to noise ratio (SNR) analysis techniques the noise floor can be predicted-determined. For instance, the two-ray ground model was used to estimate capacity in a spread spectrum cellular mobile system showed excellent results. Further, these model formulas describe the grade of service (GoS) as the probability that an arbitrary user will experience a blocked call in a lost call cleared systems. The likelihood of a call not having immediate access to a channel in a lost call delayed (LCD) system is determined. For LCD systems, the GoS is measured by the probability theory that calls will have delays greater than t seconds. The knowledge of Erlang C formula and service distribution is used to analyze GoS. It was assumed that a nearly number of users are present in the system, and that all calls in the queue ultimately are serviced. The Erlang C model also assumes a large number of channels and a large number of users with similar calling patterns. The author assumes that, typically five or more channels are considered to be a sufficiently large number of channels.

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